1. Field of the Invention
The present invention relates generally to a transistor and methods for fabricating the same, and more particularly to a transistor including an active region and methods for fabricating the same.
2. Description of the Related Art
Semiconductor devices may include an integrated circuit. Integrated circuits may include discrete devices (e.g., transistors). Because semiconductor devices may require a higher level of integration, smaller transistor gate sizes may be required. The electrical characteristics of transistors with reduced gate sizes may degrade due to a short channel effect, which may result from the reduced size of the gate. Several conventional methods exist which may reduce the short channel effect. These methods include reducing a junction depth (e.g., of a source and a drain) and increasing an effective channel length. The two above-described methods may be implemented for a recessed channel metal oxide semiconductor (MOS) transistor at the same time.
FIG. 1 is a cross-sectional view illustrating a prior art method of fabricating a MOS transistor.
Referring to FIG. 1, a buffer layer pattern 110 and a mask pattern 115 may be formed in a region of a semiconductor substrate 100. The semiconductor substrate 100 may be etched using the mask pattern 115 as an etch mask to form a trench. After a liner 250 is formed on a sidewall of the trench, an insulating layer filling the trench and covering a surface of the semiconductor substrate 100 may be formed. The insulating layer may be patterned to form a gate opening. The active region exposed in the gate opening may be isotropically etched to form a gate trench. A deposition process, a planarization process, and an etchback process may then be used to form isolation layers 605 and 610, a gate insulating layer 450, and a gate electrode 615.
However, fences (e.g., Silicon (Si) fences) may remain on other sidewalls (not shown) of the gate trench when the gate trench is formed. Fences may reduce the effective channel length, which may increase the short channel effect.
FIG. 2A is a cross sectional view illustrating a conventional method of fabricating a MOS transistor.
FIG. 2B is a cross-sectional view taken along the line I-I′ of FIG. 2A.
FIG. 2C is a cross-sectional view taken along the line II-II′ of FIG. 2A.
Referring to FIGS. 2A, 2B, and 2C, an isolation layer 25 may be formed in a region of a semiconductor substrate 21 to define an active region 22. A buffer layer pattern 31 and a mask pattern 32 may be formed on the semiconductor substrate 21 including the isolation layer 25. The active region 22 may be etched using the mask pattern 32 as an etch mask to form a gate trench 33. Fences 34 and 35 may remain on sidewalls of the gate trench 33 adjacent to the isolation layers 25.
The electrical characteristics (e.g., current, voltage, etc.) of the recessed channel MOS transistor may be determined by characteristics (e.g., length, width, depth, etc.) of the gate trench 33. Increasing the depth of the gate trench 33 may reduce the short channel effect and gate trenches (e.g., gate trench 33) may be formed at higher depths.
Referring to FIGS. 2A and 2C, the fences 34 and 35 may be formed on sidewalls of the gate trench 33 in contact with the isolation layers 25. When the remaining fences 34 and 35 are present on the sidewalls of the gate trench 33, a channel may be formed in the Si fences 34 and 35. As shown in FIGS. 2A and 2C, the fences 34 and 35 may be at a lesser depth than the depth of the gate trench 33. Thus, because a channel is formed at a lesser depth than the depth of the gate trench 33, the effective channel length may be decreased.
FIG. 2D is a cross sectional view illustrating a later step in the conventional method of fabricating the MOS transistor of FIG. 2A.
Referring to FIG. 2D, the remaining fences 34 and 35 may be removed by isotropically etching the semiconductor substrate. An etching gas and/or etching solutions may be used for the isotropic etching. As a result, the exposed surfaces of the active region 22, including the remaining fences 34 and 35, may be etched. The etch rate at the center of the gate trench 33 may be different (e.g., slower) than the etching rate at the region A. The etch rate difference may cause the gate trench 33 to be deeper and/or wider (e.g., due to excessive etching) because the etching process may continue until the fences 34 and 35 may be removed (e.g., at the slower etching rate). This process may cause sharp silicon residues in the region A of the gate trench 33 as shown in FIG. 2D.
When the sharp silicon residues are present in the region A of the gate trench 33, a field enhancement effect may occur in the region A. The field enhancement effect may cause a gate induced drain leakage (GIDL) current. The data retention characteristics of a semiconductor device such as a Dynamic Random Access Memory (DRAM) may degrade in response to the GIDL current.